Wafer Level Stacked Die Packaging

ABSTRACT

A stacked die package in which an adhesive pad separates a bottom die from a top die. The pad may be in the form of a wall of adhesive about a central hollow area. The bottom die is attached to a base with a low temperature curing adhesive or a snap cure adhesive.

The present application is a divisional application of U.S. patentapplication Ser. No. 11/874,083, filed Oct. 17, 2007, now issued as U.S.Pat. No. ______, the full disclosure of which is hereby incorporated byreference herein.

BACKGROUND OF THE INVENTION

The present invention relates to stacked microelectronic devices andmethods of manufacturing the same.

Stacked die packaging typically comes in any of three forms: pyramidconfiguration, inverted pyramid configuration and same size dieconfiguration. In a pyramid configuration the top die is smaller thanthe bottom die. The opposite is true in the inverted pyramidconfiguration. Alternatively, the dies can be the same size. In allstacked die configurations, an adhesive is typically applied to attachthe top and bottom die together. In the case of the inverted pyramidwith a larger die on top, the inclusion of a spacer is often requiredwhich introduces two separate and additional die attach steps in packageassembly processes. Spacers are made from several different types ofmaterials that include silicon and polymer based pre-defined tapes.Electrical connections are provided by bonding electrodes on the dies towires for connection to the base.

SUMMARY OF THE INVENTION

In accordance with embodiments of the invention, a stacked die packageincludes at least two microelectronic semiconductor dies, one affixed ontop of the other. An adhesive wall atop the bottom die outlines an airgap between a bottom and top die. In one embodiment, the adhesive wallis in the shape of a rectangle and forms a perimeter about a hollow areacentrally disposed above the die. In other embodiments, the adhesivewall may be C-shaped, V-shaped, H-shaped or X-shaped to name a fewconfigurations. The top die is affixed on the adhesive wall to createthe stacked dies. In a specific embodiment, the adhesive wall provides athickness between the dies in a ratio of at least 1:1 with the width ofthe wall. The stacked dies are mounted on a base. Wire bonds connectatop surface of each of the dies to the base. The stacked die packagecan be encased within a non-conductive material molded over the firstand second semiconductor dies. The package may further includeconductive balls attached to a bottom surface of the base forfacilitating electrical connections.

In accordance with a method of manufacturing, a pattern of adhesive padsis deposited on the active surface of a semiconductor wafer. Among thepossible adhesive patterns are an array of rings of adhesive or an arrayof geometrically shaped solid blocks of adhesive. The wafer isthereafter singulated to separate it into individual first semiconductordies, each die having an adhesive pad thereon. A rear surface of eachfirst semiconductor die can be attached to a base. Wire bonding may beperformed between the first semiconductor die and its respective base. Asecond semiconductor die is attached atop the adhesive pad onto thefirst semiconductor die to form a stacked die package. Wire bonding maybe further performed to electrically attach the second semiconductor dieto the base. Overmolding the first and second semiconductor die stackswith non-conductive materials encases the individual packages. In apreferred embodiment, the wafer may be backgrinded before the deposit ofa pattern of adhesive. The method may further include partially curingthe adhesive before singulating the wafer.

Stress on the die surface of the underlying die typically imparted bythe adhesive layer is reduced by using only an adhesive wall leaving anadhesive free air gap region. Application of the adhesive to the activesurface of the semiconductor wafer provides for an efficientmanufacturing process. Other objects and advantages of the inventionwill become apparent during the following description of the presentlypreferred embodiments of the invention taken in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the invention will be more readily understoodby reference to the following detailed description, taken with referenceto the accompanying drawings, in which:

FIGS. 1A and 1B are plan views of an intermediate semiconductor productin accordance with embodiments of the invention.

FIG. 2 is a schematic plan view of the product of FIG. 1A aftersingulation into individual dies.

FIG. 3 is a schematic side elevational view of a single die afterattachment to a base.

FIG. 4 is a schematic side elevational view of the die of FIG. 3 afterwire bonding.

FIG. 5 is a schematic side elevational view of the die of FIG. 4 afterattachment of the top die.

FIG. 6 is a schematic elevational view of the stacked dies of FIG. 5after wire bonding of the top die.

FIG. 7 is a schematic side elevational view of the stacked dies of FIG.6 after overmolding.

FIG. 8 is a schematic side elevational view of the stacked dies of FIG.7 after ball attachment.

FIG. 9 is a flowchart diagram of an embodiment of the invention of amethod for making stacked dies.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

In order to make a stacked die package in a mass production method, astarting material may be a semiconductor wafer as is well known in theart. The typical semiconductor wafer is made from silicon. An array ofmicroelectronic circuits is formed on the semiconductor wafer.Typically, the array of circuits is formed in rows and columns ofindividual microelectronic circuits. The semiconductor wafer includes anactive surface onto which wire connections can be made and a rearsurface for mounting. When thickness is an issue, a backgrinding processmay be performed on the wafer bearing the circuits to make it and, thus,the resulting dies thinner.

In accordance with an aspect of the present invention as seen in FIG. 9,adhesive pads 11 a, 11 b are deposited 100 onto the active surface ofthe semiconductor wafer wherein each adhesive pad 11 a, 11 b is alignedwith one of the individual microelectronic circuits. The adhesive pad 11a, 11 b is an amount of adhesive having a thickness such that it willadvantageously act as a spacer between a bottom die and top die of apackage.

The adhesive pads may be applied to the wafer in any of a number ofmethods. Such methods include screen printing or photolithography. Theadhesive material may be selected from any of a number of adhesivessuitable for use in making microelectronic components. Such adhesivesmay include, for example, polyimide or BCB (benzocyclobutene). Thethickness of the adhesive to be used as a spacer depends upon thegeometrical features of the silicon die for a given packagingapplication. For a stacked die in which the smaller die is placed ontop, a smaller thickness spacer is acceptable, for example, in the rangeof 5 to 20 microns. In an embodiment in which a larger die is placed ontop of the smaller die to form a stacked package the thickness of theadhesive may be, for example, between 50 and 75 microns. Such a thickadhesive pad may be more suitable for application through a screenprinting method. The method and products of the present invention may beused with any thickness adhesive pad that can be used to produce auseable device.

In accordance with one embodiment as shown in FIG. 1A, the adhesive pads11 a, are rings of adhesive. The adhesive forms a wall that leaves ahollow area 13 centrally disposed above each die as shown in FIG. 1A.This hollowed out central portion 13 leaves an air gap that will thusnot stress the bottom die in a manner normally associated with theadhesive. Spacers based on organic material can induce thermomechanicalshear stress on the top side of the bottom silicon die in a stacked diepackage. The magnitude of this shear stress will depend on the materialproperties, geometry of the spacer and interface adhesion area. Thisshear stress has potential to cause delamination and/or cracking in diepassivation and/or inner layer structures inside the silicon die. Theadhesive rings reduce the adhesion area and are thus designed to reducethese shear stresses. The adhesive acts as a wall that forms theperimeter about the hollow central portion. In the embodiment of FIG.1A, the ring of adhesive is in the shape of a rectangle. It iscontemplated that in specific embodiments, a minimal aspect ratio forthickness (height) of the wall to width of the wall should be 1 to 1.The actual aspect ratio of the adhesive wall will depend upon thegeometrical features of the bottom die and type of application. Suchwalls may be used to create pads in shapes other than a ring that stillcreate an air gap and derive similar advantages of reduced stress. Suchshapes are innumerable including C-shaped, H-shaped, V shaped orX-shaped among others.

In accordance with an alternative embodiment such as that shown in FIG.1B, the adhesive pads 11 b are geometrically shaped as solid blocks ofadhesive. The shape shown in FIG. 1B is that of a rectangular block ofadhesive. Certainly, an oval or other shapes may be used as well.

In accordance with a preferred embodiment, each adhesive pad is orientedover a microelectronic circuit but within boundaries set by bond pads 15for use along the periphery of a die. Thus, the bond pads 15 for themicroelectronic circuit are exposed and accessible outside the peripheryof the adhesive pad. Once the adhesive pads have been deposited, anintermediate semiconductor product has been completed for further use inthe manufacturing of stacked die packaging.

The method of manufacture continues with the step of partially curing102 the adhesive to bring it to its B-stage. B-stage is an intermediatestage in a thermosetting resin reaction in which the plastic remains ina soft state. The intermediate semiconductor product is then ready forsingulation. The singulation process 104 typically involves sawing thewafer into individual dies 20 as shown in FIG. 2. Each die 20 includes amicroelectronic circuit and the adhesive pad 11 a, 11 b that had beendeposited thereon.

The individual dies may then be picked and placed onto a base 30. Asuitable pickup nozzle is used to accommodate the circuit with adhesivepad thereon. A snap cure or low temperature curing adhesive 32 on thebase 30 attaches 106 the bottom of the die 20 to the base. The base 30may be a substrate or lead frame or other suitable base for supporting astacked die package. The snap cure or low temperature curing adhesive 32may then be cured without fully curing the adhesive pad 11 a, 11 b onthe die 20. The curing may take place at a lower temperature than willcure the adhesive pad or the curing can take place in a short time spansuch that the adhesive pad does not cure. Standard die attach materials,such as ABLESTIK 84-1, are cured at temperatures well below full curefor adhesives such as polyimide or BCB. For example, a die attachmaterial might be cured at temperatures between 125° C. and 150° C. forapproximately one hour. The BCB or polyimide used for the adhesive padmay, on the other hand, cure at over 300° C. for more than 30 minutes toan hour.

After attaching the bottom die to the base, the adhesive attaching thedie to the base is cured without curing the adhesive pad 108. Thus, theadhesive pad may remain in its B-stage during this low temperature orquick curing. At this point, wire bonding 110 can be performed toconnect bond pads on the bottom die to the base, as shown in FIG. 4.

A top die 50 is then ready for attachment 112 above the bottom die 20.The top die 50 is placed on the adhesive pad 11 a, 11 b as shown in FIG.5. Full curing 114 of the B-stage adhesive pad is then performed tosecurely attach the bottom and top dies of the stacked die package. Wirebonding 116 may then be completed from the top die 50 to the base 30 asshown in FIG. 6. Overmolding 118 encases the stacked die package in anonconductive material as shown in FIG. 7. Overmolding may be performed,for example, using a standard transfer molding process. Depending on thetype of package and base that has been used, at this point ballattachment to the bottom of the base may be performed in order toprovide conductive points for accessing the microelectronics as shown inFIG. 8.

In accordance with embodiments of the invention, an air gap 80 remainsdisposed between the bottom die and the top die when a wall of adhesivewas used to form the adhesive pad. In particular, when a ring ofadhesive 11 a is formed the air gap 80 is centrally disposed. Thisrelieves that central area of stress associated with an adhesiveconnection.

Of course, it should be understood that various changes andmodifications to the preferred embodiments described above will beapparent to those skilled in the art. For example, a stacked die packagein accordance with the invention can be made with a smaller or largertop die with respect to the bottom die. Moreover, the base of thepackage may be a semiconductor substrate or a lead frame depending uponthe desired package. Furthermore, additional layers of dies may beincluded so that multiple dies are stacked using the described methods.These and other changes can be made without departing from the spiritand scope of the invention and without diminishing its attendantadvantages. It is therefore intended that such changes and modificationsbe covered by the following claims.

1. A stacked die package comprising: a first microelectronicsemiconductor die; an adhesive pad atop the die; a secondmicroelectronic semiconductor die affixed atop the adhesive pad; and abase on which the first microelectronic semiconductor die is attached byan adhesive that cures at a lower temperature than the adhesive in theadhesive pad.
 2. The stacked die package of claim 1, further comprisingwire bonds connected between a top surface of the first microelectronicsemiconductor die and the base.
 3. The stacked die package of claim 2,further comprising wire bonds connected between a top surface of thesecond microelectronic semiconductor die and the base.
 4. The stackeddie package of claim 3, further comprising nonconductive material moldedover the first and second semiconductor dies.
 5. The stacked die packageof claim 4, further comprising conductive balls attached to a bottomsurface of the base.
 6. The stacked die package of claim 1, wherein theadhesive pad forms a perimeter about a hollow area centrally disposedabove the die.
 7. The stacked die package of claim 6, wherein theadhesive pad is in the shape of a rectangular wall.
 8. The stacked diepackage of claim 6, wherein the adhesive pad has a width on the die anda thickness from the die to a top of the pad, wherein a ratio of thethickness to the width is at least 1:1 and the second microelectronicsemiconductor die is separated from the first microelectronicsemiconductor die by the wall thickness.
 9. The stacked die package ofclaim 1, wherein the adhesive attaching the first microelectronicsemiconductor die to the base comprises a low temperature curingadhesive, which cures at temperatures between 125° C. and 150° C.
 10. Astacked die package comprising: a first microelectronic semiconductordie; an adhesive pad atop the die; a second microelectronicsemiconductor die affixed atop the adhesive pad; and a base on which thefirst microelectronic semiconductor die is attached by a snap cureadhesive, which cures more quickly than the adhesive in the adhesivepad.
 11. The stacked die package of claim 10, further comprising wirebonds connected between a top surface of the first microelectronicsemiconductor die and the base.
 12. The stacked die package of claim 11,further comprising wire bonds connected between a top surface of thesecond microelectronic semiconductor die and the base.
 13. The stackeddie package of claim 12, further comprising nonconductive materialmolded over the first and second semiconductor dies.
 14. The stacked diepackage of claim 13, further comprising conductive balls attached to abottom surface of the base.
 15. The stacked die package of claim 10,wherein the adhesive pad forms a perimeter about a hollow area centrallydisposed above the die.
 16. The stacked die package of claim 15, whereinthe adhesive pad is in the shape of a rectangular wall.
 17. The stackeddie package of claim 15, wherein the adhesive pad has a width on the dieand a thickness from the die to a top of the wall, wherein a ratio ofthe thickness to the width is at least 1:1 and the secondmicroelectronic semiconductor die is separated from the firstmicroelectronic semiconductor die by the wall thickness.